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Add shiftL and shiftR operators for signed and unsigned. Update name of shiftl and...
[matthijs/master-project/cλash.git]
/
clash
/
CLasH
/
HardwareTypes.hs
diff --git
a/clash/CLasH/HardwareTypes.hs
b/clash/CLasH/HardwareTypes.hs
index dbb0ecac94cc93a0dcd446686fb01714a4d9d894..572a64e7f66154842d1fcb6887a71ba0f6a83a8d 100644
(file)
--- a/
clash/CLasH/HardwareTypes.hs
+++ b/
clash/CLasH/HardwareTypes.hs
@@
-2,11
+2,13
@@
module CLasH.HardwareTypes
( module Types
module CLasH.HardwareTypes
( module Types
+ , module Data.Param.Integer
, module Data.Param.Vector
, module Data.Param.Index
, module Data.Param.Signed
, module Data.Param.Unsigned
, module Prelude
, module Data.Param.Vector
, module Data.Param.Index
, module Data.Param.Signed
, module Data.Param.Unsigned
, module Prelude
+ , module Data.Bits
, Bit(..)
, State(..)
, hwand
, Bit(..)
, State(..)
, hwand
@@
-21,10
+23,12
@@
module CLasH.HardwareTypes
import qualified Prelude as P
import Prelude (Bool(..),Num(..),Eq(..),Ord(..),snd,fst,otherwise,(&&),(||),not)
import Types
import qualified Prelude as P
import Prelude (Bool(..),Num(..),Eq(..),Ord(..),snd,fst,otherwise,(&&),(||),not)
import Types
+import Data.Param.Integer (HWBits(..))
import Data.Param.Vector
import Data.Param.Index
import Data.Param.Signed
import Data.Param.Unsigned
import Data.Param.Vector
import Data.Param.Index
import Data.Param.Signed
import Data.Param.Unsigned
+import Data.Bits hiding (shiftL,shiftR)
import Language.Haskell.TH.Lift
import Data.Typeable
import Language.Haskell.TH.Lift
import Data.Typeable