Reflect moving TFVec and TFP Integers into clash in sourcefiles related to builtin...

[matthijs/master-project/cλash.git] / cλash / CLasH / VHDL / Constants.hs

diff --git a/cλash/CLasH/VHDL/Constants.hs b/cλash/CLasH/VHDL/Constants.hs
index 54a294115f9308dce7ece44404d90a06b328d08a..c70ca71a04258b589b76798815a9a509ec4c9bb3 100644 (file)
--- a/cλash/CLasH/VHDL/Constants.hs
+++ b/cλash/CLasH/VHDL/Constants.hs
@@ -1,7 +1,22 @@
 module CLasH.VHDL.Constants where
-  
+
+-- VHDL Imports  
 import qualified Language.VHDL.AST as AST
 
+-- | A list of all builtin functions. Partly duplicates the name table
+-- in VHDL.Generate, but we can't use that map everywhere due to
+-- circular dependencie.
+builtinIds = [ exId, replaceId, headId, lastId, tailId, initId, takeId, dropId
+             , selId, plusgtId, ltplusId, plusplusId, mapId, zipWithId, foldlId
+             , foldrId, zipId, unzipId, shiftlId, shiftrId, rotlId, rotrId
+             , concatId, reverseId, iteratenId, iterateId, generatenId, generateId
+             , emptyId, singletonId, copynId, copyId, lengthTId, nullId
+             , hwxorId, hwandId, hworId, hwnotId, equalityId, inEqualityId, ltId
+             , lteqId, gtId, gteqId, boolOrId, boolAndId, plusId, timesId
+             , negateId, minusId, fromSizedWordId, fromIntegerId, resizeWordId
+             , resizeIntId, sizedIntId, smallIntegerId, fstId, sndId, blockRAMId
+             , splitId, minimumId, fromRangedWordId 
+             ]
 --------------
 -- Identifiers
 --------------
@@ -235,6 +250,9 @@ fstId = "fst"
 sndId :: String
 sndId = "snd"
 
+splitId :: String
+splitId = "split"
+
 -- Equality Operations
 equalityId :: String
 equalityId = "=="
@@ -260,6 +278,9 @@ boolOrId = "||"
 boolAndId :: String
 boolAndId = "&&"
 
+boolNot :: String
+boolNot = "not"
+
 -- Numeric Operations
 
 -- | plus operation identifier
@@ -280,7 +301,10 @@ minusId = "-"
 
 -- | convert sizedword to ranged
 fromSizedWordId :: String
-fromSizedWordId = "fromSizedWord"
+fromSizedWordId = "fromUnsigned"
+
+fromRangedWordId :: String
+fromRangedWordId = "fromIndex"
 
 toIntegerId :: String
 toIntegerId = "to_integer"
@@ -307,10 +331,10 @@ smallIntegerId :: String
 smallIntegerId = "smallInteger"
 
 sizedIntId :: String
-sizedIntId = "SizedInt"
+sizedIntId = "Signed"
 
 tfvecId :: String
-tfvecId = "TFVec"
+tfvecId = "Vector"
 
 blockRAMId :: String
 blockRAMId = "blockRAM"
@@ -372,4 +396,4 @@ stringTM = AST.unsafeVHDLBasicId "string"
 
 -- | tup VHDLName suffix
 tupVHDLSuffix :: AST.VHDLId -> AST.Suffix
-tupVHDLSuffix id = AST.SSimple id
\ No newline at end of file
+tupVHDLSuffix id = AST.SSimple id