update cabal file to upload to hackage

[matthijs/master-project/cλash.git] / cλash / CLasH / VHDL.hs

diff --git a/cλash/CLasH/VHDL.hs b/cλash/CLasH/VHDL.hs
index 8429a5786810ae52b6b72146722fcd1d44b72462..56342fc2ce7df52d35d1caef448fea5381282ee4 100644 (file)
--- a/cλash/CLasH/VHDL.hs
+++ b/cλash/CLasH/VHDL.hs
@@ -6,38 +6,22 @@ module CLasH.VHDL where
 -- Standard modules
 import qualified Data.Map as Map
 import qualified Maybe
-import qualified Control.Monad as Monad
 import qualified Control.Arrow as Arrow
-import qualified Control.Monad.Trans.State as State
-import qualified Data.Monoid as Monoid
 import Data.Accessor
-import Data.Accessor.MonadState as MonadState
-import Debug.Trace
+import qualified Data.Accessor.Monad.Trans.State as MonadState
 
--- ForSyDe
+-- VHDL Imports
 import qualified Language.VHDL.AST as AST
 
 -- GHC API
-import CoreSyn
---import qualified Type
-import qualified Name
-import qualified Var
-import qualified IdInfo
-import qualified TyCon
-import qualified DataCon
---import qualified CoreSubst
-import qualified CoreUtils
-import Outputable ( showSDoc, ppr )
+import qualified CoreSyn
 
 -- Local imports
 import CLasH.Translator.TranslatorTypes
 import CLasH.VHDL.VHDLTypes
 import CLasH.VHDL.VHDLTools
-import CLasH.Utils.Pretty
-import CLasH.Utils.Core.CoreTools
 import CLasH.VHDL.Constants
 import CLasH.VHDL.Generate
-import CLasH.VHDL.Testbench
 
 createDesignFiles ::
   [CoreSyn.CoreBndr] -- ^ Top binders
@@ -82,16 +66,17 @@ createTypesPackage ::
   -- ^ The id and content of the types package
  
 createTypesPackage = do
-  tyfuns <- getA (tsType .> tsTypeFuns)
-  let tyfun_decls = mkBuiltInShow ++ (map snd $ Map.elems tyfuns)
-  ty_decls <- getA (tsType .> tsTypeDecls)
+  tyfuns <- MonadState.get (tsType .> tsTypeFuns)
+  let tyfun_decls = mkBuiltInShow ++ map snd (Map.elems tyfuns)
+  ty_decls_maybes <- MonadState.get (tsType .> tsTypeDecls)
+  let ty_decls = Maybe.catMaybes ty_decls_maybes
   let subProgSpecs = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec) tyfun_decls
   let type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ ty_decls ++ subProgSpecs)
   let type_package_body = AST.LUPackageBody $ AST.PackageBody typesId tyfun_decls
-  return $ (mkVHDLBasicId "types", AST.DesignFile ieee_context [type_package_dec, type_package_body])
+  return (mkVHDLBasicId "types", AST.DesignFile ieee_context [type_package_dec, type_package_body])
   where
     tfvec_index_decl = AST.PDISD $ AST.SubtypeDec tfvec_indexTM tfvec_index_def
-    tfvec_range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit "-1") (AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerTM) (AST.NSimple $ highId) Nothing)
+    tfvec_range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit "-1") (AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerTM) (AST.NSimple highId) Nothing)
     tfvec_index_def = AST.SubtypeIn integerTM (Just tfvec_range)
 
 -- Create a use foo.bar.all statement. Takes a list of components in the used