Fixed VHDL Type generation, vhdlTy now uses HType's to generate VHDL Types. Logic...

[matthijs/master-project/cλash.git] / cλash / CLasH / Utils / GhcTools.hs

diff --git a/cλash/CLasH/Utils/GhcTools.hs b/cλash/CLasH/Utils/GhcTools.hs
index 373e9cf6827f3db91f0877ef73370ec7757ff912..c11b5486ffc0424aaaf6c3ca60084fc1fe8ce623 100644 (file)
--- a/cλash/CLasH/Utils/GhcTools.hs
+++ b/cλash/CLasH/Utils/GhcTools.hs
@@ -217,9 +217,9 @@ findInitStates statec annsc mod = do
     extractInits (InitState x)  = Just x
     extractInits _              = Nothing
     zipMWith :: (a -> b -> c) -> (Maybe [a]) -> [b] -> (Maybe [c])
-    zipMwith _ Nothing _ = Nothing
+    zipMWith _ Nothing   _  = Nothing
     zipMWith f (Just as) bs = Just $ zipWith f as bs
-    
+
 -- | Make a complete spec out of a three conditions
 findSpec ::
   (Var.Var -> GHC.Ghc Bool) -> (Var.Var -> GHC.Ghc Bool) -> (Var.Var -> GHC.Ghc [CLasHAnn]) -> (Var.Var -> GHC.Ghc Bool)