Fixed VHDL Type generation, vhdlTy now uses HType's to generate VHDL Types. Logic...

[matthijs/master-project/cλash.git] / cλash / CLasH / Translator / TranslatorTypes.hs

diff --git a/cλash/CLasH/Translator/TranslatorTypes.hs b/cλash/CLasH/Translator/TranslatorTypes.hs
index 12ca6ed8ea9313f59ecd035e8d2e299a6d58bbc6..2591e666f0b3491b93b8f8baaced8d993b77998d 100644 (file)
--- a/cλash/CLasH/Translator/TranslatorTypes.hs
+++ b/cλash/CLasH/Translator/TranslatorTypes.hs
@@ -46,19 +46,21 @@ instance Eq OrdType where
 instance Ord OrdType where
   compare (OrdType a) (OrdType b) = Type.tcCmpType a b
 
-data HType = StdType OrdType |
-             ADTType String [HType] |
+data HType = AggrType String [HType] |
              EnumType String [String] |
              VecType Int HType |
+             UVecType HType |
              SizedWType Int |
              RangedWType Int |
              SizedIType Int |
-             BuiltinType String
-  deriving (Eq, Ord)
+             BuiltinType String |
+             StateType
+  deriving (Eq, Ord, Show)
 
 -- A map of a Core type to the corresponding type name, or Nothing when the
 -- type would be empty.
-type TypeMap = Map.Map HType (Maybe (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn))
+type TypeMapRec   = Maybe (AST.VHDLId, Maybe (Either AST.TypeDef AST.SubtypeIn))
+type TypeMap      = Map.Map HType TypeMapRec
 
 -- A map of a vector Core element type and function name to the coressponding
 -- VHDLId of the function and the function body.
@@ -70,7 +72,7 @@ data TypeState = TypeState {
   -- | A map of Core type -> VHDL Type
   tsTypes_      :: TypeMap,
   -- | A list of type declarations
-  tsTypeDecls_  :: [AST.PackageDecItem],
+  tsTypeDecls_  :: [Maybe AST.PackageDecItem],
   -- | A map of vector Core type -> VHDL type function
   tsTypeFuns_   :: TypeFunMap,
   tsTfpInts_    :: TfpIntMap,