Fixed VHDL Type generation, vhdlTy now uses HType's to generate VHDL Types. Logic...

[matthijs/master-project/cλash.git] / cλash / CLasH / Translator.hs

diff --git a/cλash/CLasH/Translator.hs b/cλash/CLasH/Translator.hs
index e2993d260548ad4a83bd9938c8f53b49a678c803..8884506ea47f27f80a0b3a93bae20384711e0159 100644 (file)
--- a/cλash/CLasH/Translator.hs
+++ b/cλash/CLasH/Translator.hs
@@ -33,6 +33,7 @@ import CLasH.Utils
 import CLasH.Utils.Core.CoreTools
 import CLasH.Utils.GhcTools
 import CLasH.VHDL
+import CLasH.VHDL.VHDLTools
 import CLasH.VHDL.Testbench
 
 -- | Turn Haskell to VHDL, Usings Strings to indicate the Top Entity, Initial
@@ -128,7 +129,7 @@ runTranslatorSession env session = do
   -- on the compiler dir of ghc suggests that 'z' is not used to generate
   -- a unique supply anywhere.
   uniqSupply <- UniqSupply.mkSplitUniqSupply 'z'
-  let init_typestate = TypeState Map.empty [] Map.empty Map.empty env
+  let init_typestate = TypeState builtin_types [] Map.empty Map.empty env
   let init_state = TranslatorState uniqSupply init_typestate Map.empty Map.empty 0 Map.empty Map.empty Map.empty
   return $ State.evalState session init_state