Have reduceCoreListToHsList work with simplified modules

[matthijs/master-project/cλash.git] / cλash / CLasH / Translator.hs

diff --git a/cλash/CLasH/Translator.hs b/cλash/CLasH/Translator.hs
index b61f5f942b8ba7b62eb0ea8200045b295899ef08..c120edc9badd448ee71837540c98d4e89adec115 100644 (file)
--- a/cλash/CLasH/Translator.hs
+++ b/cλash/CLasH/Translator.hs
@@ -103,7 +103,7 @@ moduleToVHDL env cores specs = do
     -- Create a testbench for any entry that has test input
     mkTest (_, _, Nothing) = return Nothing
     mkTest (top, _, Just input) = do
-      bndr <- createTestbench Nothing input top
+      bndr <- createTestbench Nothing cores input top
       return $ Just bndr
 
 -- Run the given translator session. Generates a new UniqSupply for that