Add builtin blockRAM primitive

[matthijs/master-project/cλash.git] / cλash / CLasH / HardwareTypes.hs

diff --git a/cλash/CLasH/HardwareTypes.hs b/cλash/CLasH/HardwareTypes.hs
index 682cd05c46fbd2a1718216b3847d30e9b42360f2..c3eaf4396ef0eb2c65c991cfabdeef9eacd2a986 100644 (file)
--- a/cλash/CLasH/HardwareTypes.hs
+++ b/cλash/CLasH/HardwareTypes.hs
@@ -1,4 +1,4 @@
-{-# LANGUAGE TemplateHaskell, DeriveDataTypeable #-}
+{-# LANGUAGE TemplateHaskell, DeriveDataTypeable, FlexibleContexts, TypeFamilies, TypeOperators #-}
 
 module CLasH.HardwareTypes
   ( module Types
@@ -14,6 +14,9 @@ module CLasH.HardwareTypes
   , hwor
   , hwxor
   , hwnot
+  , RAM
+  , MemState
+  , blockRAM
   ) where
 
 import qualified Prelude as P
@@ -57,4 +60,27 @@ Low `hwxor` High = High
 _ `hwxor` _      = Low
 
 hwnot High = Low
-hwnot Low  = High
\ No newline at end of file
+hwnot Low  = High
+
+type RAM s a          = Vector (s :+: D1) a
+
+type MemState s a      = State (RAM s a)
+
+blockRAM :: 
+  (NaturalT s
+  ,PositiveT (s :+: D1)
+  ,((s :+: D1) :>: s) ~ True ) =>
+  (MemState s a) -> 
+  a ->
+  RangedWord s ->
+  RangedWord s ->
+  Bit -> 
+  ((MemState s a), a )
+blockRAM (State mem) data_in rdaddr wraddr wrenable = 
+  ((State mem'), data_out)
+  where
+    data_out  = mem!rdaddr
+    -- Only write data_in to memory if write is enabled
+    mem' = case wrenable of
+      Low   ->  mem
+      High  ->  replace mem wraddr data_in