Added subtype declarations to TypeMap, removed SubtypeMap.

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 9b48579600e86e4977f871a79f4898a82a3f27f4..cc842897a873f28416974c98fc212be9609eca85 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -43,10 +43,7 @@ instance Ord OrdType where
   compare (OrdType a) (OrdType b) = Type.tcCmpType a b
 
 -- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
-
--- A map of a Core type to the corresponding VHDL subtype
-type SubTypeMap = Map.Map OrdType (AST.VHDLId, AST.SubtypeDec)
+type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
 
 -- A map of a vector Core type to the coressponding VHDL functions
 type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
@@ -60,8 +57,6 @@ type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
 data VHDLSession = VHDLSession {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
-  -- | A map of Core type -> VHDL SubType
-  vsSubTypes_   :: SubTypeMap,
   -- | A map of vector Core type -> VHDL type function
   vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,