Redo the global (state) structure of the translator.

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 74084864dc8c3c9f8d8a1aa27a433e4a7cf8132a..948b3a1447b0320f01c2599b12b15875d8d4112d 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -1,10 +1,22 @@
 --
 -- Some types used by the VHDL module.
 --
+{-# LANGUAGE TemplateHaskell #-}
 module VHDLTypes where
 
+-- Standard imports
+import qualified Control.Monad.Trans.State as State
+import qualified Data.Map as Map
+import Data.Accessor
+import qualified Data.Accessor.Template
+
+-- GHC API imports
+import qualified Type
+
+-- ForSyDe imports
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
+-- Local imports
 import FlattenTypes
 import HsValueMap
 
@@ -18,7 +30,34 @@ type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
 data Entity = Entity {
   ent_id     :: AST.VHDLId,           -- The id of the entity
   ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
-  ent_res    :: VHDLSignalMap,        -- A mapping of the function result to port names
-  ent_decl   :: Maybe AST.EntityDec,  -- The actual entity declaration. Can be empty for builtin functions.
-  ent_pkg_decl :: Maybe AST.PackageDec -- A package declaration with types for this entity
+  ent_res    :: VHDLSignalMap         -- A mapping of the function result to port names
 } deriving (Show);
+
+-- A orderable equivalent of CoreSyn's Type for use as a map key
+newtype OrdType = OrdType Type.Type
+instance Eq OrdType where
+  (OrdType a) == (OrdType b) = Type.tcEqType a b
+instance Ord OrdType where
+  compare (OrdType a) (OrdType b) = Type.tcCmpType a b
+
+-- A map of a Core type to the corresponding type name (and optionally, it's
+-- declaration for non-primitive types).
+type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
+
+-- A map of a Haskell function to a hardware signature
+type SignatureMap = Map.Map HsFunction Entity
+
+data VHDLSession = VHDLSession {
+  -- | A map of Core type -> VHDL Type
+  vsTypes_ :: TypeMap,
+  -- | A map of HsFunction -> hardware signature (entity name, port names,
+  --   etc.)
+  vsSignatures_ :: SignatureMap
+}
+
+-- Derive accessors
+$( Data.Accessor.Template.deriveAccessors ''VHDLSession )
+
+type VHDLState = State.State VHDLSession
+
+-- vim: set ts=8 sw=2 sts=2 expandtab: