Remove type parameterisation of SignalMap.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index 9516fdd2eb137f0bc75900e13a98df52df70b191..32279fdea471a0c055a50ccb39cd6bd8491fd9de 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -176,8 +176,8 @@ getSignalId info =
 
 -- | Transforms a flat function application to a VHDL component instantiation.
 mkCompInsSm ::
-  [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture
-  -> FApp UnnamedSignal         -- | The application to look at.
+  [(SignalId, SignalInfo)] -- | The signals in the current architecture
+  -> FApp                       -- | The application to look at.
   -> VHDLState AST.CompInsSm    -- | The corresponding VHDL component instantiation.
 
 mkCompInsSm sigs app = do
@@ -195,8 +195,8 @@ mkCompInsSm sigs app = do
   return $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
 
 mkAssocElems :: 
-  [(UnnamedSignal, SignalInfo)] -- | The signals in the current architecture
-  -> FApp UnnamedSignal         -- | The application to look at.
+  [(SignalId, SignalInfo)] -- | The signals in the current architecture
+  -> FApp                       -- | The application to look at.
   -> Entity                     -- | The entity to map against.
   -> [AST.AssocElem]            -- | The resulting port maps
 
@@ -217,7 +217,7 @@ mkAssocElems sigmap app entity =
     sigs      = (map (lookupSigName sigmap) (arg_sigs ++ res_sigs))
 
 -- | Look up a signal in the signal name map
-lookupSigName :: [(UnnamedSignal, SignalInfo)] -> UnnamedSignal -> String
+lookupSigName :: [(SignalId, SignalInfo)] -> SignalId -> String
 lookupSigName sigs sig = name
   where
     info = Maybe.fromMaybe