Add a Type to a Literal SignalExpr.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index 67ef0c79dd08327a8938109285e99997f4003d56..08034192bf6ced1d4e813f094c4be9b3cbf3417c 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -275,7 +275,7 @@ mkConcSm _ sigs (UncondDef src dst) _ =
       case expr of
         (EqLit id lit) ->
           (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
-        (Literal lit) ->
+        (Literal lit _) ->
           AST.PrimLit lit
         (Eq a b) ->
           (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)