Make the Alu example use 4-bit SizedWord as data.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 396dfbc40e8e03769fea16d673281a0baeb01865..c4bcdbdf02084e9ad8ee8d1c2faf320873e983eb 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -49,7 +49,7 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
-  makeVHDL "Alu.hs" "register_bank" True
+  makeVHDL "Alu.hs" "exec" True
 
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do