Use a different approach for marking SigUses.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 53befc228e6ef947107b72141d9cb7c713fd5606..c16406be3aef2781484251c56a21d3e5fb394f54 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -45,7 +45,7 @@ main = do
   -- Load the module
   core <- loadModule "Adders.hs"
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["sfull_adder"]
+  vhdl <- moduleToVHDL core ["dff"]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"