Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 0f60277671f99b646ec427deb8fd82ce92d53169..1786332678717097892bd84c7b2ac66c0badefba 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -52,8 +52,8 @@ import FlattenTypes
 import VHDLTypes
 import qualified VHDL
 
--- main = do
---   makeVHDL "Alu.hs" "exec" True
+main = do
+  makeVHDL "Adders.hs" "highordtest2" True
 
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do