Mark all signals as ports or states when appropriate.

[matthijs/master-project/cλash.git] / Pretty.hs

diff --git a/Pretty.hs b/Pretty.hs
index 65645760959aa7f314633f0848c7a14617d39a5b..7c9840450339be35f57184f950824042fcc41283 100644 (file)
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -61,9 +61,11 @@ instance Pretty SignalInfo where
       ppname (Just name) = text ":" <> text name
 
 instance Pretty SigUse where
-  pPrint SigPort     = text "P"
+  pPrint SigPortIn   = text "PI"
+  pPrint SigPortOut  = text "PO"
   pPrint SigInternal = text "I"
-  pPrint SigState    = text "S"
+  pPrint (SigStateOld n) = text "SO:" <> int n
+  pPrint (SigStateNew n) = text "SN:" <> int n
   pPrint SigSubState = text "s"
 
 instance Pretty VHDLSession where