Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project

[matthijs/master-project/cλash.git] / Main.hs

diff --git a/Main.hs b/Main.hs
index be0a0a077f5496d7c9f3c06daa4fd58ae12779b7..be48aa3bb3d86aaac2b0ac7e4aaf4fc6614a79ac 100644 (file)
--- a/Main.hs
+++ b/Main.hs
@@ -3,4 +3,4 @@ module Main where
 import Translator
 
 main = do
-  makeVHDL "Alu.hs" "exec" True
\ No newline at end of file
+  makeVHDL "Adders.hs" "highordtest" True
\ No newline at end of file