Add the type-alias Vector for TFVec to HardwareTypes, and don't export TFVec.TFVec...

[matthijs/master-project/cλash.git] / HighOrdAlu.hs

diff --git a/HighOrdAlu.hs b/HighOrdAlu.hs
index 39bf4d91ef7dbbe131354945f925ef9b7ba9262e..e5dcbfddfd22eb96021e03315b462d41c16dcef6 100644 (file)
--- a/HighOrdAlu.hs
+++ b/HighOrdAlu.hs
@@ -26,11 +26,11 @@ anyset f s a b = constant (f a' b') a b
 
 xhwor = hwor
 
-type Op n e = (TFVec n e -> TFVec n e -> TFVec n e)
+type Op n e = (Vector n e -> Vector n e -> Vector n e)
 type Opcode = Bit
 
 {-# ANN sim_input TestInput#-}
-sim_input :: [(Opcode, TFVec D4 (SizedInt D8), TFVec D4 (SizedInt D8))]
+sim_input :: [(Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8))]
 sim_input = [ (High,  $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8])))
             , (High,  $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8])))
             , (Low,   $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8]))) ]
@@ -38,14 +38,14 @@ sim_input = [ (High,  $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3
 {-# ANN actual_alu InitState #-}
 initstate = High
 
-alu :: Op n e -> Op n e -> Opcode -> TFVec n e -> TFVec n e -> TFVec n e
+alu :: Op n e -> Op n e -> Opcode -> Vector n e -> Vector n e -> Vector n e
 alu op1 op2 opc a b =
   case opc of
     Low -> op1 a b
     High -> op2 a b
 
 {-# ANN actual_alu TopEntity #-}
-actual_alu :: (Opcode, TFVec D4 (SizedInt D8), TFVec D4 (SizedInt D8)) -> TFVec D4 (SizedInt D8)
+actual_alu :: (Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8)) -> Vector D4 (SizedInt D8)
 --actual_alu = alu (constant Low) andop
 actual_alu (opc, a, b) = alu (anyset (+) (0 :: SizedInt D8)) (andop (-)) opc a b