Add support for translating designs defined over multiple modules

[matthijs/master-project/cλash.git] / HighOrdAlu.hs

diff --git a/HighOrdAlu.hs b/HighOrdAlu.hs
index e5dcbfddfd22eb96021e03315b462d41c16dcef6..bdbdc3c28821a8aae361e33d445cffb5c05d41bc 100644 (file)
--- a/HighOrdAlu.hs
+++ b/HighOrdAlu.hs
@@ -6,28 +6,7 @@ import qualified Prelude as P
 import CLasH.HardwareTypes
 import CLasH.Translator.Annotations
 
-constant :: NaturalT n => e -> Op n e
-constant e a b = copy e
-
-invop :: Op n Bit
-invop a b = map hwnot a
-
-andop :: (e -> e -> e) -> Op n e
-andop f a b = zipWith f a b
-
--- Is any bit set?
---anyset :: (PositiveT n) => Op n Bit
-anyset :: NaturalT n => (e -> e -> e) -> e -> Op n e
---anyset a b = copy undefined (a' `hwor` b')
-anyset f s a b = constant (f a' b') a b
-  where 
-    a' = foldl f s a
-    b' = foldl f s b
-
-xhwor = hwor
-
-type Op n e = (Vector n e -> Vector n e -> Vector n e)
-type Opcode = Bit
+import HighOrdAluOps
 
 {-# ANN sim_input TestInput#-}
 sim_input :: [(Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8))]