Really revert all of the recent rotating changes.

[matthijs/master-project/cλash.git] / Alu.hs

diff --git a/Alu.hs b/Alu.hs
index 1c60c0414886cbb975d18fb994a286beb46e1c24..7171a6549d4a216f7ffb876eacdc4d8db5e22571 100644 (file)
--- a/Alu.hs
+++ b/Alu.hs
@@ -30,6 +30,7 @@ type RegAddr = Bit
 type RegisterBankState = State (Word, Word)
 --data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
 
+{-# NOINLINE register_bank #-}
 register_bank :: 
   RegAddr -- ^ Address
   -> Bit -- ^ Write Enable
@@ -37,19 +38,21 @@ register_bank ::
   -> RegisterBankState -> -- State
   (RegisterBankState, Word) -- (State', Output)
 
-register_bank addr we d (State s) =
-  case we of
-    Low -> -- Read
-      let
-        o = case addr of Low -> fst s; High -> snd s
-      in (State s, o) -- Don't change state
-    High -> -- Write
-      let
-        (r0, r1) = s
-        r0' = case addr of Low -> d; High -> r0
-        r1' = case addr of High -> d; Low -> r1
-        s' = (r0', r1')
-      in (State s', 0) -- Don't output anything useful
+register_bank addr we d (State s) = (State s', o)
+  where
+    s' = case we of
+      Low -> s -- Read
+      High -> -- Write
+        let
+          (r0, r1) = s
+          r0' = case addr of Low -> d; High -> r0
+          r1' = case addr of High -> d; Low -> r1
+        in (r0', r1')
+    o = case we of
+      -- Read
+      Low -> case addr of Low -> fst s; High -> snd s
+      -- Write
+      High -> 0 -- Don't output anything useful
 
 -- ALU
 
@@ -59,8 +62,8 @@ alu :: AluOp -> Word -> Word -> Word
 {-# NOINLINE alu #-}
 --alu High a b = a `hwand` b
 --alu Low a b = a `hwor` b
-alu High a b = a P.+ b
-alu Low a b = a P.- b
+alu High a b = a + b
+alu Low a b = a - b
 
 type ExecState = State (RegisterBankState, Word, Word)
 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)