Update the hardware models a bit.

[matthijs/master-project/cλash.git] / Adders.hs

diff --git a/Adders.hs b/Adders.hs
index c49ba810ce1ae4768ac2bd7efd673d1c198a0a28..e6676e94888f3ce0bec9c9a489672da8288200e0 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -1,8 +1,16 @@
-module Adders (main, no_carry_adder) where
+module Adders where
 import Bits
+import qualified Sim
 import Language.Haskell.Syntax
+import qualified Data.TypeLevel as TypeLevel
+import qualified Data.Param.FSVec as FSVec
 
-main = do show_add exp_adder; show_add rec_adder;
+mainIO f = Sim.simulateIO (Sim.stateless f) ()
+
+-- This function is from Sim.hs, but we redefine it here so it can get inlined
+-- by default.
+stateless :: (i -> o) -> (i -> () -> ((), o))
+stateless f = \i s -> (s, f i)
 
 show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
   where
@@ -10,18 +18,108 @@ show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displ
     b = [Low, Low, Low, High]
     (s, c) = f (a, b)
 
--- Combinatoric no-carry adder
+mux2 :: Bit -> (Bit, Bit) -> Bit
+mux2 Low (a, b) = a
+mux2 High (a, b) = b
+
+-- Not really an adder, but this is nice minimal hardware description
+wire :: Bit -> Bit
+wire a = a
+
+bus :: (TypeLevel.Pos len) => BitVec len -> BitVec len
+bus v = v
+
+bus_4 :: BitVec TypeLevel.D4 -> BitVec TypeLevel.D4
+bus_4 v = v
+
+{-
+inv_n :: (Pos len) => BitVec len -> BitVec len
+inv_n v =
+  --FSVec.map hwnot v
+  inv_n_rec v
+
+class Inv vec where
+  inv_n_rec :: vec -> vec
+
+instance (Pos len) => Inv (BitVec len) where
+  inv_n_rec v = 
+    h FSVec.+> t
+    where
+      h = FSVec.head v
+      t = FSVec.tail v
+
+instance Inv (BitVec D0) where
+  inv_n_rec v = v
+-}
+-- Not really an adder either, but a slightly more complex example
+inv :: Bit -> Bit
+inv a = hwnot a
+
+-- Not really an adder either, but a slightly more complex example
+invinv :: Bit -> Bit
+invinv a = hwnot (hwnot a)
+
+-- Not really an adder either, but a slightly more complex example
+dup :: Bit -> (Bit, Bit)
+dup a = (a, a)
+
+-- Not really an adder either, but a simple stateful example (D-flipflop)
+dff :: Bit -> Bit -> (Bit, Bit)
+dff d s = (s', q)
+  where
+    q = s
+    s' = d
+
+type ShifterState = (Bit, Bit, Bit, Bit)
+shifter :: Bit -> ShifterState -> (ShifterState, Bit)
+shifter i (a, b, c, d) =
+  (s', d)
+  where
+    s' = (i, a, b, c)
+
+{-# NOINLINE shifter_en #-}
+shifter_en :: Bit -> Bit-> ShifterState -> (ShifterState, Bit)
+shifter_en High i (a, b, c, d) =
+  (s', d)
+  where
+    s' = (i, a, b, c)
+
+shifter_en Low i s@(a, b, c, d) =
+  (s, d)
+
+-- Two multiplexed shifters
+type ShiftersState = (ShifterState, ShifterState)
+shifters :: Bit -> Bit -> ShiftersState -> (ShiftersState, Bit)
+shifters sel i (sa, sb) =
+  (s', out)
+  where
+    (sa', outa) = shifter_en sel i sa
+    (sb', outb) = shifter_en (hwnot sel) i sb
+    s' = (sa', sb')
+    out = if sel == High then outa else outb
+
+-- Combinatoric stateless no-carry adder
 -- A -> B -> S
 no_carry_adder :: (Bit, Bit) -> Bit
 no_carry_adder (a, b) = a `hwxor` b
 
--- Combinatoric (one-bit) full adder
+-- Combinatoric stateless half adder
+-- A -> B -> (S, C)
+half_adder :: (Bit, Bit) -> (Bit, Bit)
+{-# NOINLINE half_adder #-}
+half_adder (a, b) = 
+  ( a `hwxor` b, a `hwand` b )
+
+-- Combinatoric stateless full adder
 -- (A, B, C) -> (S, C)
 full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
 full_adder (a, b, cin) = (s, c)
   where
-    s = a `hwxor` b `hwxor` cin
-    c = a `hwand` b `hwor` (cin `hwand` (a `hwxor` b))
+    (s1, c1) = half_adder(a, b)
+    (s, c2)  = half_adder(s1, cin)
+    c        = c1 `hwor` c2
+
+sfull_adder = stateless full_adder
 
 -- Four bit adder
 -- Explicit version