Generate a state proc for a stateful function.
[matthijs/master-project/cλash.git] / cλash / CLasH / VHDL /
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-rw-r--r-- 6532 Constants.hs
-rw-r--r-- 74518 Generate.hs
-rw-r--r-- 7370 Testbench.hs
-rw-r--r-- 33318 VHDLTools.hs
-rw-r--r-- 1011 VHDLTypes.hs