Fixed VHDL Type generation, vhdlTy now uses HType's to generate VHDL Types. Logic...
[matthijs/master-project/cλash.git] / cλash / CLasH / Translator /
drwxr-xr-x   ..
-rw-r--r-- 610 Annotations.hs
-rw-r--r-- 4540 TranslatorTypes.hs