From edb200f40c64361b24ecc8af187f724bd5d6d9bb Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Thu, 6 Aug 2009 16:21:32 +0200 Subject: [PATCH] Don't generate input ports for State arguments. --- "c\316\273ash/CLasH/VHDL/Generate.hs" | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs" index 4de6b40..e71e0d9 100644 --- "a/c\316\273ash/CLasH/VHDL/Generate.hs" +++ "b/c\316\273ash/CLasH/VHDL/Generate.hs" @@ -46,7 +46,8 @@ getEntity fname = Utils.makeCached fname tsEntities $ do expr <- Normalize.getNormalized fname -- Strip off lambda's, these will be arguments let (args, letexpr) = CoreSyn.collectBinders expr - args' <- mapM mkMap args + -- Generate ports for all non-state types + args' <- mapM mkMap (filter (not.hasStateType) args) -- There must be a let at top level let (CoreSyn.Let binds (CoreSyn.Var res)) = letexpr res' <- mkMap res -- 2.30.2