From fa8761cd4d31ca41f79de1bd0861a1552c9274f8 Mon Sep 17 00:00:00 2001 From: Christiaan Baaij Date: Mon, 22 Jun 2009 17:27:14 +0200 Subject: [PATCH] Updated support for RangedWords, Requires new branch of ForSyDe --- Generate.hs | 10 +++++----- VHDL.hs | 5 +++-- "c\316\273ash.cabal" | 2 +- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/Generate.hs b/Generate.hs index 23e4a2c..d3c05ab 100644 --- a/Generate.hs +++ b/Generate.hs @@ -53,7 +53,7 @@ genUnconsVectorFuns elemTM vectorTM = replaceVar = AST.VarDec resId (AST.SubtypeIn vectorTM - (Just $ AST.IndexConstraint + (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar) lengthId Nothing) AST.:-: @@ -88,7 +88,7 @@ genUnconsVectorFuns elemTM vectorTM = initVar = AST.VarDec resId (AST.SubtypeIn vectorTM - (Just $ AST.IndexConstraint + (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar) lengthId Nothing) AST.:-: @@ -106,7 +106,7 @@ genUnconsVectorFuns elemTM vectorTM = tailVar = AST.VarDec resId (AST.SubtypeIn vectorTM - (Just $ AST.IndexConstraint + (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar) lengthId Nothing) AST.:-: @@ -125,7 +125,7 @@ genUnconsVectorFuns elemTM vectorTM = takeVar = AST.VarDec resId (AST.SubtypeIn vectorTM - (Just $ AST.IndexConstraint + (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") ((AST.PrimName (AST.NSimple nPar)) AST.:-: (AST.PrimLit "1")) ])) @@ -141,7 +141,7 @@ genUnconsVectorFuns elemTM vectorTM = dropVar = AST.VarDec resId (AST.SubtypeIn vectorTM - (Just $ AST.IndexConstraint + (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar) lengthId Nothing) AST.:-: diff --git a/VHDL.hs b/VHDL.hs index ecf6406..92df267 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -624,7 +624,7 @@ mk_vector_ty len el_ty ty = do elem_types_map <- getA vsElemTypes el_ty_tm <- vhdl_ty el_ty let ty_id = mkVHDLExtId $ "vector-"++ (AST.fromVHDLId el_ty_tm) ++ "-0_to_" ++ (show len) - let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))] + let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))] let existing_elem_ty = (fmap fst) $ Map.lookup (OrdType el_ty) elem_types_map case existing_elem_ty of Just t -> do @@ -645,7 +645,8 @@ mk_natural_ty :: -> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created. mk_natural_ty min_bound max_bound ty = do let ty_id = mkVHDLExtId $ "nat_" ++ (show min_bound) ++ "_to_" ++ (show max_bound) - let ty_def = AST.SubtypeIn naturalTM (Nothing) + let range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit $ (show min_bound)) (AST.PrimLit $ (show max_bound)) + let ty_def = AST.SubtypeIn naturalTM (Just range) return (ty_id, ty_def) diff --git "a/c\316\273ash.cabal" "b/c\316\273ash.cabal" index 798b281..7d2d670 100644 --- "a/c\316\273ash.cabal" +++ "b/c\316\273ash.cabal" @@ -12,7 +12,7 @@ author: Christiaan Baaij & Matthijs Kooijman stability: alpha maintainer: christiaan.baaij@gmail.com & matthijs@stdin.nl build-depends: base > 4, syb, ghc, ghc-paths, transformers, haskell98, - ForSyDe, regex-posix ,data-accessor-template, pretty, + ForSyDe > 3.0, regex-posix ,data-accessor-template, pretty, data-accessor, containers, prettyclass, tfp > 0.3, tfvec, QuickCheck, template-haskell -- 2.30.2