From f330640bc6a6652d5d841ce147596e08e05e316c Mon Sep 17 00:00:00 2001
From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Wed, 4 Mar 2009 22:10:58 +0100
Subject: [PATCH] Add some hardware models using vectors (FSVec).

---
 Adders.hs | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/Adders.hs b/Adders.hs
index 7243b50..f07c8e9 100644
--- a/Adders.hs
+++ b/Adders.hs
@@ -2,6 +2,8 @@ module Adders where
 import Bits
 import qualified Sim
 import Language.Haskell.Syntax
+import Data.TypeLevel
+import qualified Data.Param.FSVec as FSVec
 
 mainIO f = Sim.simulateIO (Sim.stateless f) ()
 
@@ -24,6 +26,31 @@ mux2 High (a, b) = b
 wire :: Bit -> Bit
 wire a = a
 
+bus :: (Pos len) => BitVec len -> BitVec len
+bus v = v
+
+bus_4 :: BitVec D4 -> BitVec D4
+bus_4 v = v
+
+{-
+inv_n :: (Pos len) => BitVec len -> BitVec len
+inv_n v =
+  --FSVec.map hwnot v
+  inv_n_rec v
+
+class Inv vec where
+  inv_n_rec :: vec -> vec
+
+instance (Pos len) => Inv (BitVec len) where
+  inv_n_rec v = 
+    h FSVec.+> t
+    where
+      h = FSVec.head v
+      t = FSVec.tail v
+
+instance Inv (BitVec D0) where
+  inv_n_rec v = v
+-}
 -- Not really an adder either, but a slightly more complex example
 inv :: Bit -> Bit
 inv a = hwnot a
-- 
2.30.2