From e7f89819c61188a732c8f011d74d783800e88da8 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Wed, 12 Aug 2009 17:28:17 +0200 Subject: [PATCH 1/1] Revert "Put mkAssocElems in the TranslatorSession." MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This reverts commit 374a42ba3cf333ae53fa1d992620d25286641ae2. Conflicts: cλash/CLasH/VHDL/Testbench.hs cλash/CLasH/VHDL/VHDLTools.hs --- "c\316\273ash/CLasH/VHDL/Generate.hs" | 4 ++-- "c\316\273ash/CLasH/VHDL/Testbench.hs" | 3 ++- "c\316\273ash/CLasH/VHDL/VHDLTools.hs" | 4 ++-- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs" index 0e5186f..3f81f8f 100644 --- "a/c\316\273ash/CLasH/VHDL/Generate.hs" +++ "b/c\316\273ash/CLasH/VHDL/Generate.hs" @@ -833,7 +833,7 @@ genApplication dst f args = do -- TODO: Using show here isn't really pretty, but we'll need some -- unique-ish value... let label = "comp_ins_" ++ (either show prettyShow) dst - portmaps <- mkAssocElems args' ((either varToVHDLName id) dst) signature + let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature return ([mkComponentInst label entity_id portmaps], [f]) False -> do -- Not a top level binder, so this must be a local variable reference. @@ -892,7 +892,7 @@ genApplication dst f args = do -- TODO: Using show here isn't really pretty, but we'll need some -- unique-ish value... let label = "comp_ins_" ++ (either show prettyShow) dst - portmaps <- mkAssocElems args' ((either varToVHDLName id) dst) signature + let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature return ([mkComponentInst label entity_id portmaps], [f]) False -> do -- Not a top level binder, so this must be a local variable reference. diff --git "a/c\316\273ash/CLasH/VHDL/Testbench.hs" "b/c\316\273ash/CLasH/VHDL/Testbench.hs" index 4f20f6c..98c5b46 100644 --- "a/c\316\273ash/CLasH/VHDL/Testbench.hs" +++ "b/c\316\273ash/CLasH/VHDL/Testbench.hs" @@ -1,3 +1,4 @@ +-- -- Functions to create a VHDL testbench from a list of test input. -- module CLasH.VHDL.Testbench where @@ -81,7 +82,7 @@ createTestbenchArch mCycles stimuli top testent= do let finalIDecs = iDecs ++ [AST.SigDec clockId std_logicTM (Just $ AST.PrimLit "'0'"), AST.SigDec resetId std_logicTM (Just $ AST.PrimLit "'0'")] - portmaps <- mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature + let portmaps = mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature let mIns = mkComponentInst "totest" entId portmaps (stimuliAssigns, stimuliDecs, cycles, used) <- createStimuliAssigns mCycles stimuli (head iIds) let finalAssigns = (AST.CSSASm (AST.NSimple resetId AST.:<==: diff --git "a/c\316\273ash/CLasH/VHDL/VHDLTools.hs" "b/c\316\273ash/CLasH/VHDL/VHDLTools.hs" index 36d35e3..b289501 100644 --- "a/c\316\273ash/CLasH/VHDL/VHDLTools.hs" +++ "b/c\316\273ash/CLasH/VHDL/VHDLTools.hs" @@ -88,9 +88,9 @@ mkAssocElems :: [AST.Expr] -- ^ The argument that are applied to function -> AST.VHDLName -- ^ The binder in which to store the result -> Entity -- ^ The entity to map against. - -> TranslatorSession [AST.AssocElem] -- ^ The resulting port maps + -> [AST.AssocElem] -- ^ The resulting port maps mkAssocElems args res entity = - return $ arg_maps ++ (Maybe.maybeToList res_map_maybe) + arg_maps ++ (Maybe.maybeToList res_map_maybe) where arg_ports = ent_args entity res_port_maybe = ent_res entity -- 2.30.2