From e0db471a3cc20af68785dfe321b8eb3db6fa1b9d Mon Sep 17 00:00:00 2001
From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Tue, 10 Mar 2009 17:58:07 +0100
Subject: [PATCH] Add a TODO.

---
 VHDL.hs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/VHDL.hs b/VHDL.hs
index 572e221..c952ddd 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -375,6 +375,7 @@ mk_fsvec_ty ty args = do
   let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "16")]
   let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty
   let ty_dec = AST.TypeDec ty_id ty_def
+  -- TODO: Check name uniqueness
   State.modify (Map.insert (OrdType ty) (ty_id, ty_dec))
   return ty_id
 
-- 
2.30.2