From d440d5946729bd07e47ef2f3fed58bbe1284f8fa Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Mon, 22 Jun 2009 15:13:23 +0200 Subject: [PATCH] Remove the old builtin function support. Its now replaced by a new structure, no longer needing external VHDL files. --- VHDL.hs | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/VHDL.hs b/VHDL.hs index 4db7445..ab7ee22 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -56,7 +56,7 @@ createDesignFiles binds = map (Arrow.second $ AST.DesignFile full_context) units where - init_session = VHDLSession Map.empty Map.empty Map.empty builtin_funcs globalNameTable + init_session = VHDLSession Map.empty Map.empty Map.empty Map.empty globalNameTable (units, final_session) = State.runState (createLibraryUnits binds) init_session tyfun_decls = Map.elems (final_session ^.vsTypeFuns) @@ -702,28 +702,6 @@ bndrToString = OccName.occNameString . Name.nameOccName . Var.varName nameToString :: Name.Name -> String nameToString = OccName.occNameString . Name.nameOccName --- | A consise representation of a (set of) ports on a builtin function ---type PortMap = HsValueMap (String, AST.TypeMark) --- | A consise representation of a builtin function -data BuiltIn = BuiltIn String [(String, AST.TypeMark)] (String, AST.TypeMark) - --- | Translate a list of concise representation of builtin functions to a --- SignatureMap -mkBuiltins :: [BuiltIn] -> SignatureMap -mkBuiltins = Map.fromList . map (\(BuiltIn name args res) -> - (name, - Entity (VHDL.mkVHDLBasicId name) (map toVHDLSignalMapElement args) (toVHDLSignalMapElement res)) - ) - -builtin_hsfuncs = Map.keys builtin_funcs -builtin_funcs = mkBuiltins - [ - BuiltIn "hwxor" [("a", VHDL.bit_ty), ("b", VHDL.bit_ty)] ("o", VHDL.bit_ty), - BuiltIn "hwand" [("a", VHDL.bit_ty), ("b", VHDL.bit_ty)] ("o", VHDL.bit_ty), - BuiltIn "hwor" [("a", VHDL.bit_ty), ("b", VHDL.bit_ty)] ("o", VHDL.bit_ty), - BuiltIn "hwnot" [("a", VHDL.bit_ty)] ("o", VHDL.bit_ty) - ] - recordlabels = map (\c -> mkVHDLBasicId [c]) ['A'..'Z'] -- | Map a port specification of a builtin function to a VHDL Signal to put in -- 2.30.2