From c38002cdfd1ec55ffcd6661d7ac2d6c44d220d87 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Tue, 23 Jun 2009 14:54:24 +0200 Subject: [PATCH] Ignore cast expressions when generating VHDL. --- VHDL.hs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/VHDL.hs b/VHDL.hs index eb45420..b2d5b30 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -264,6 +264,11 @@ mkConcSm :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process -> VHDLState [AST.ConcSm] -- ^ The corresponding VHDL component instantiations. + +-- Ignore Cast expressions, they should not longer have any meaning as long as +-- the type works out. +mkConcSm (bndr, Cast expr ty) = mkConcSm (bndr, expr) + mkConcSm (bndr, app@(CoreSyn.App _ _))= do let (CoreSyn.Var f, args) = CoreSyn.collectArgs app let valargs' = filter isValArg args -- 2.30.2