From b98d46bc13dc17a8783dbf844fb34fb9b0f2be49 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Tue, 10 Mar 2009 16:00:55 +0100 Subject: [PATCH] Add support for builtin functions again. --- Translator.hs | 33 +++------------------------------ VHDL.hs | 30 +++++++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 31 deletions(-) diff --git a/Translator.hs b/Translator.hs index 1ecbdb9..a94e3f4 100644 --- a/Translator.hs +++ b/Translator.hs @@ -268,8 +268,10 @@ resolvFunc :: resolvFunc hsfunc = do flatfuncmap <- getA tsFlatFuncs - -- Don't do anything if there is already a flat function for this hsfunc. + -- Don't do anything if there is already a flat function for this hsfunc or + -- when it is a builtin function. Monad.unless (Map.member hsfunc flatfuncmap) $ do + Monad.unless (elem hsfunc VHDL.builtin_hsfuncs) $ do -- TODO: Builtin functions -- New function, resolve it core <- getA tsCoreModule @@ -352,33 +354,4 @@ splitTupleType ty = Nothing Nothing -> Nothing --- | A consise representation of a (set of) ports on a builtin function -type PortMap = HsValueMap (String, AST.TypeMark) --- | A consise representation of a builtin function -data BuiltIn = BuiltIn String [PortMap] PortMap - --- | Map a port specification of a builtin function to a VHDL Signal to put in --- a VHDLSignalMap -toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap -toVHDLSignalMap = fmap (\(name, ty) -> Just (VHDL.mkVHDLId name, ty)) - --- | Translate a concise representation of a builtin function to something --- that can be put into FuncMap directly. -{- -addBuiltIn :: BuiltIn -> TranslatorState () -addBuiltIn (BuiltIn name args res) = do - addFunc hsfunc - setEntity hsfunc entity - where - hsfunc = HsFunction name (map useAsPort args) (useAsPort res) - entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing Nothing - -builtin_funcs = - [ - BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)), - BuiltIn "hwand" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)), - BuiltIn "hwor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)), - BuiltIn "hwnot" [(Single ("a", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)) - ] --} -- vim: set ts=8 sw=2 sts=2 expandtab: diff --git a/VHDL.hs b/VHDL.hs index 9a51c7a..8fe3cfe 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -26,6 +26,7 @@ import VHDLTypes import Flatten import FlattenTypes import TranslatorTypes +import HsValueMap import Pretty createDesignFiles :: @@ -36,7 +37,7 @@ createDesignFiles flatfuncmap = -- TODO: Output types map (Arrow.second $ AST.DesignFile context) units where - init_session = VHDLSession Map.empty Map.empty + init_session = VHDLSession Map.empty builtin_funcs (units, final_session) = State.runState (createLibraryUnits flatfuncmap) init_session context = [ @@ -374,3 +375,30 @@ mkVHDLId s = ('_':_) -> "_" _ -> cs ) . List.group + +-- | A consise representation of a (set of) ports on a builtin function +type PortMap = HsValueMap (String, AST.TypeMark) +-- | A consise representation of a builtin function +data BuiltIn = BuiltIn String [PortMap] PortMap + +-- | Translate a list of concise representation of builtin functions to a +-- SignatureMap +mkBuiltins :: [BuiltIn] -> SignatureMap +mkBuiltins = Map.fromList . map (\(BuiltIn name args res) -> + (HsFunction name (map useAsPort args) (useAsPort res), + Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res)) + ) + +builtin_hsfuncs = Map.keys builtin_funcs +builtin_funcs = mkBuiltins + [ + BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)), + BuiltIn "hwand" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)), + BuiltIn "hwor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)), + BuiltIn "hwnot" [(Single ("a", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)) + ] + +-- | Map a port specification of a builtin function to a VHDL Signal to put in +-- a VHDLSignalMap +toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap +toVHDLSignalMap = fmap (\(name, ty) -> Just (mkVHDLId name, ty)) -- 2.30.2