From b4b8def2facb3d3bf92ee02a499405efdf986324 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Tue, 23 Jun 2009 12:53:47 +0200 Subject: [PATCH] Always add a clk port map on instantiations. This changes make the translator generate synthesizable VHDL again. --- VHDL.hs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/VHDL.hs b/VHDL.hs index 00b5dda..4f8d105 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -313,8 +313,9 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do label = "comp_ins_" ++ bndrToString bndr -- Add a clk port if we have state --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk" + clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk" --portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else []) - portmaps = mkAssocElems args bndr signature + portmaps = clk_port : mkAssocElems args bndr signature in return [AST.CSISm $ AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)] details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details -- 2.30.2