From a628d8d874df6af54c6d4f766012bac117eea037 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Mon, 2 Feb 2009 10:01:37 +0100 Subject: [PATCH] Write the resulting vhdl to file. --- Translator.hs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Translator.hs b/Translator.hs index 11e425d..4992d1c 100644 --- a/Translator.hs +++ b/Translator.hs @@ -26,6 +26,7 @@ import qualified Monad -- ForSyDe to get access to these modules. import qualified ForSyDe.Backend.VHDL.AST as AST import qualified ForSyDe.Backend.VHDL.Ppr +import qualified ForSyDe.Backend.VHDL.FileIO import qualified ForSyDe.Backend.Ppr -- This is needed for rendering the pretty printed VHDL import Text.PrettyPrint.HughesPJ (render) @@ -49,6 +50,7 @@ main = -- Turn bind into VHDL let vhdl = State.evalState (mkVHDL binds) (VHDLSession 0 []) liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr vhdl + liftIO $ ForSyDe.Backend.VHDL.FileIO.writeDesignFile vhdl "../vhdl/vhdl/output.vhdl" return () where -- Turns the given bind into VHDL -- 2.30.2