From 527a6aa73e730b0837d9cec13554ceaacb0a2fca Mon Sep 17 00:00:00 2001
From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Tue, 10 Mar 2009 17:50:45 +0100
Subject: [PATCH] Filter out dots from generated type id's.

---
 VHDL.hs | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/VHDL.hs b/VHDL.hs
index c1b42b3..ae72368 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -369,7 +369,8 @@ mk_fsvec_ty ty args = do
   -- Assume there are two type arguments
   let [len, el_ty] = args 
   -- TODO: Find actual number
-  let ty_id = mkVHDLId ("vector_" ++ (show len))
+  -- Construct the type id, but filter out dots (since these are not allowed).
+  let ty_id = mkVHDLId $ filter (/='.') ("vector_" ++ (show len))
   -- TODO: Use el_ty
   let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "16")]
   let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty
-- 
2.30.2