From 23a9ac963f8123a6fecf5105492f8be5e2da8190 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Apr 2008 14:19:30 +0200 Subject: [PATCH] * No longer keep a global variable with the current stage number, but pass it as an argument to the functions that need it. This also replaces the stage_odd parameter. * No longer loop through the needed stages, since the Montium sequencer can't change the twiddle memory mask dynamically. Instead, call the (new) do_regular_stage() function four times manually, with constant stage numbers that the optimizer can roll out. --- FFT.mc | 68 ++++++++++++++++++++++++++++------------------------------ 1 file changed, 33 insertions(+), 35 deletions(-) diff --git a/FFT.mc b/FFT.mc index 5969315..4a80cfa 100644 --- a/FFT.mc +++ b/FFT.mc @@ -6,7 +6,6 @@ #include "FFT.h" -int stage = 1; /** * Executes a single butterfly on ALU 0-3. The inputs are the words taken from * in, which will be read on various inputs of ALU 0-3. Outputs will be @@ -76,7 +75,7 @@ INLINE void write_output_regular(struct mems m, struct bf_out res, bool second_h * read input a from memory b and v.v. If not, * simply read a from memory a and b from memory b. */ -INLINE struct bf_in read_input_regular(struct mems m, bool cycle_odd, bool stage_odd) { +INLINE struct bf_in read_input_regular(struct mems m, bool cycle_odd, int stage) { struct bf_in in; /* Swap memory a and b during the odd cycles */ if (cycle_odd) { @@ -110,11 +109,10 @@ INLINE struct bf_in read_input_regular(struct mems m, bool cycle_odd, bool stage } /** - * Initializes the addresses for writing the outputs. - * @param stage_odd True if this is an odd stage. - * @param second_half True if we are initing halfway a stage. + * Initializes the addresses for reading the inputs and twiddel factors. + * Should be called once at the start of each stage. */ -INLINE void init_input_addresses_regular(struct mems m, bool stage_odd) { +INLINE void init_input_addresses_regular(struct mems m) { /* We simply start reading at address 0 incrementally */ set_base(m.input_a_im, 0); set_base(m.input_b_re, 0); @@ -134,7 +132,7 @@ INLINE void init_input_addresses_regular(struct mems m, bool stage_odd) { * Initializes the addresses for reading the inputs. This function must be * called twice per stage, since halfway the stage the addressing changes. */ -INLINE void init_output_addresses_regular(struct mems m, bool stage_odd, bool second_half) { +INLINE void init_output_addresses_regular(struct mems m, bool second_half) { /* * For the second half of the stage, the starting addresses are * reversed. write_output_regular above will also swap the output @@ -163,7 +161,7 @@ INLINE void init_output_addresses_regular(struct mems m, bool stage_odd, bool se } } -INLINE void do_half_regular_stage(struct mems m, bool stage_odd, bool second_half){ +INLINE void do_half_regular_stage(struct mems m, int stage, bool second_half){ /* * We are doing two cycles in each iteration, so we can alternate the * cycle_odd argument (which only works with constants, I don't expect @@ -179,10 +177,10 @@ INLINE void do_half_regular_stage(struct mems m, bool stage_odd, bool second_hal */ /* Initialize output addresses, this must be done twice per stage */ - init_output_addresses_regular(m, stage_odd, second_half); + init_output_addresses_regular(m, second_half); /* First cycle (no previous output to write) */ - struct bf_in in = read_input_regular(m, EVEN_CYCLE, stage_odd); + struct bf_in in = read_input_regular(m, EVEN_CYCLE, stage); struct bf_out out = butterfly(in); /* Now, do half a single stage. That means N_t / 4 cycles. Since we do 2 @@ -194,7 +192,7 @@ INLINE void do_half_regular_stage(struct mems m, bool stage_odd, bool second_hal write_output_regular(m, out, second_half); /* Odd cycle */ - in = read_input_regular(m, ODD_CYCLE, second_half); + in = read_input_regular(m, ODD_CYCLE, stage); out = butterfly(in); next_cycle(); @@ -202,7 +200,7 @@ INLINE void do_half_regular_stage(struct mems m, bool stage_odd, bool second_hal write_output_regular(m, out, second_half); /* Even cycle */ - in = read_input_regular(m, EVEN_CYCLE, second_half); + in = read_input_regular(m, EVEN_CYCLE, stage); out = butterfly(in); } while (loop_next(LC2)); @@ -210,7 +208,7 @@ INLINE void do_half_regular_stage(struct mems m, bool stage_odd, bool second_hal write_output_regular(m, out, second_half); /* Last cycle */ - in = read_input_regular(m, ODD_CYCLE, second_half); + in = read_input_regular(m, ODD_CYCLE, stage); out = butterfly(in); next_cycle(); @@ -222,9 +220,15 @@ INLINE void do_half_regular_stage(struct mems m, bool stage_odd, bool second_hal next_cycle(); } -INLINE struct mems init_mem_mapping(bool stage_odd){ +/** + * Assign the input and output memories, based on the current stage. Also + * assigns the twiddle memories, but those are fixed. + */ +INLINE struct mems init_mem_mapping(int stage){ struct mems res; - if (stage_odd) { + /* Use left memories for input on odd (ie, first) + * stages and right memories on even stages. */ + if ((stage % 2) == 0) { res.input_a_re = alloc_mem(P0M1); res.input_a_im = alloc_mem(P1M1); res.input_b_re = alloc_mem(P2M1); @@ -249,27 +253,21 @@ INLINE struct mems init_mem_mapping(bool stage_odd){ return res; } + +INLINE void do_regular_stage(int stage) +{ + struct mems m = init_mem_mapping(stage); + init_input_addresses_regular(m); + /* do_half_regular_stage will init output addresses */ + next_cycle(); + do_half_regular_stage(m, stage, FIRST_HALF); + do_half_regular_stage(m, stage, SECOND_HALF); +} void run() { do { freeze(); } while (gpi(0) == 0); - struct mems m; - /* We need to do n_t regular stages. Since we do two stages each - * iteration, we'll do n_t / 2 iterations (and a -1 because we check after looping) */ - init_loop(LC1, (PARAM_n_t / 2) - 1); - do { - m = init_mem_mapping(EVEN_STAGE); - init_input_addresses_regular(m, EVEN_STAGE); - /* do_half_regular_stage will init output addresses */ - next_cycle(); - do_half_regular_stage(m, EVEN_STAGE, FIRST_HALF); - do_half_regular_stage(m, EVEN_STAGE, SECOND_HALF); - stage++; - next_cycle(); - init_input_addresses_regular(m, ODD_STAGE); - m = init_mem_mapping(ODD_STAGE); - next_cycle(); - do_half_regular_stage(m, ODD_STAGE, FIRST_HALF); - do_half_regular_stage(m, ODD_STAGE, SECOND_HALF); - stage++; - } while (loop_next(LC1)); + do_regular_stage(1); + do_regular_stage(2); + do_regular_stage(3); + do_regular_stage(4); } -- 2.30.2