From 51a7bd0bb429d112154578fdd1dfd706e6e01f6e Mon Sep 17 00:00:00 2001 From: Christiaan Baaij Date: Fri, 14 Aug 2009 16:34:16 +0200 Subject: [PATCH] Ignore casts that just repack state. Don't make VHDL for them, their type is empty --- "c\316\273ash/CLasH/VHDL/Generate.hs" | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs" index 7faeb01..8732164 100644 --- "a/c\316\273ash/CLasH/VHDL/Generate.hs" +++ "b/c\316\273ash/CLasH/VHDL/Generate.hs" @@ -187,7 +187,10 @@ mkConcSm :: -- Ignore Cast expressions, they should not longer have any meaning as long as --- the type works out. +-- the type works out. Throw away state repacking +mkConcSm (bndr, to@(CoreSyn.Cast from ty)) + | hasStateType to && hasStateType from + = return ([],[]) mkConcSm (bndr, CoreSyn.Cast expr ty) = mkConcSm (bndr, expr) -- Simple a = b assignments are just like applications, but without arguments. -- 2.30.2