From 57a2771de1d155d9c382614531f88882ed74325b Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Wed, 4 Mar 2009 11:35:08 +0100 Subject: [PATCH] Map the clk port on stateful function applications. --- VHDL.hs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/VHDL.hs b/VHDL.hs index 80b069b..b448672 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -203,7 +203,9 @@ mkConcSm sigs (FApp hsfunc args res) = do (funcEntity fdata) let entity_id = ent_id entity label <- uniqueName (AST.fromVHDLId entity_id) - let portmaps = mkAssocElems sigs args res entity + -- Add a clk port if we have state + let clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLId "clk") "clk" + let portmaps = mkAssocElems sigs args res entity ++ (if hasState hsfunc then [clk_port] else []) return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps) mkConcSm sigs (UncondDef src dst) = do -- 2.30.2