From 01012813997b2f30e4c1df4d43c1e7e5de0135a8 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Tue, 23 Jun 2009 11:49:57 +0200 Subject: [PATCH] Don't generate a signal for the output port. --- VHDL.hs | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/VHDL.hs b/VHDL.hs index 92df267..d2fbc63 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -196,10 +196,12 @@ createArchitecture (fname, expr) = do -- Strip off lambda's, these will be arguments let (args, letexpr) = CoreSyn.collectBinders expr -- There must be a let at top level - let (CoreSyn.Let (CoreSyn.Rec binds) res) = letexpr + let (CoreSyn.Let (CoreSyn.Rec binds) (Var res)) = letexpr - -- Create signal declarations for all internal and state signals - sig_dec_maybes <- mapM (mkSigDec' . fst) binds + -- Create signal declarations for all binders in the let expression, except + -- for the output port (that will already have an output port declared in + -- the entity). + sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds) let sig_decs = Maybe.catMaybes $ sig_dec_maybes statements <- Monad.mapM mkConcSm binds -- 2.30.2