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Mark all signals as ports or states when appropriate.
[matthijs/master-project/cλash.git] / VHDLTypes.hs
2009-02-16 Matthijs KooijmanLet mkCompInsSm look up the actual VHDL entity id. blob | commitdiff | raw
2009-02-13 Matthijs KooijmanPut a TypeMark in a VHDLSignalmap. blob | commitdiff | raw | diff to current
2009-02-13 Matthijs KooijmanAdd the VHDLTypes module blob | commitdiff | raw | diff to current
The Cλash compiler