Create state procs for state signals.
[matthijs/master-project/cλash.git] / VHDLTypes.hs
2009-02-16 Matthijs KooijmanLet mkCompInsSm look up the actual VHDL entity id.
2009-02-13 Matthijs KooijmanPut a TypeMark in a VHDLSignalmap.
2009-02-13 Matthijs KooijmanAdd the VHDLTypes module