From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Thu, 19 Feb 2009 10:35:13 +0000 (+0100)
Subject: Further reduce main and add a makeVHDL function.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=f39903a05a540e2438805792ac39a89dac1c8e99;hp=1e30fe04f4c285970ad2d5e23930dd935b4214fa;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Further reduce main and add a makeVHDL function.
---

diff --git a/Translator.hs b/Translator.hs
index 9838060..ddd09fc 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -42,10 +42,14 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
+  makeVHDL "Alu.hs" "salu"
+
+makeVHDL :: String -> String -> IO ()
+makeVHDL filename name = do
   -- Load the module
-  core <- loadModule "Alu.hs"
+  core <- loadModule filename
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["salu"]
+  vhdl <- moduleToVHDL core [name]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"