From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Tue, 23 Jun 2009 13:37:51 +0000 (+0200)
Subject: Map generations always maps clk port
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=ee39139fa25cb75c8acc40b10d90f6482b8d1b30;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Map generations always maps clk port

gen function is butt ugly, needs to be fixed
---

diff --git a/Generate.hs b/Generate.hs
index 637ef27..9a3a48c 100644
--- a/Generate.hs
+++ b/Generate.hs
@@ -31,23 +31,35 @@ genMapCall ::
   -> AST.GenerateSm -- | The resulting generate statement
 genMapCall len entity [arg, res] = genSm
   where
-    label = AST.unsafeVHDLBasicId ("mapVector" ++ (AST.fromVHDLId res))
+    label = mkVHDLExtId ("mapVector" ++ (AST.fromVHDLId res))
     nPar  = AST.unsafeVHDLBasicId "n"
     range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
     genScheme = AST.ForGn nPar range
     entity_id = ent_id entity
     argport = map (Monad.liftM fst) (ent_args entity)
     resport = (Monad.liftM fst) (ent_res entity)
-    inport = mkAssocElem (head argport) arg
-    outport = mkAssocElem resport res
-    portmaps = Maybe.catMaybes [inport,outport]
+    inport = mkAssocElemI (head argport) arg
+    outport = mkAssocElemI resport res
+    clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
+    portmaps = Maybe.catMaybes [inport,outport,clk_port]
+    portname = mkVHDLExtId ("map" ++ (AST.fromVHDLId entity_id))
     portmap = AST.CSISm $ AST.CompInsSm (AST.unsafeVHDLBasicId "map12") (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
     genSm = AST.GenerateSm label genScheme [] [portmap]
     -- | Create an VHDL port -> signal association
-    mkAssocElem :: Maybe AST.VHDLId -> AST.VHDLId -> Maybe AST.AssocElem
-    mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NIndexed (AST.IndexedName 
+    mkAssocElemI :: Maybe AST.VHDLId -> AST.VHDLId -> Maybe AST.AssocElem
+    mkAssocElemI (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NIndexed (AST.IndexedName 
                     (AST.NSimple signal) [AST.PrimName $ AST.NSimple nPar])))
+    mkAssocElemI Nothing _ = Nothing
+    mkAssocElem :: Maybe AST.VHDLId -> String -> Maybe AST.AssocElem
+    mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLExtId signal))) 
     mkAssocElem Nothing _ = Nothing
+    mkVHDLExtId :: String -> AST.VHDLId
+    mkVHDLExtId s = 
+      AST.unsafeVHDLExtId $ strip_invalid s
+      where 
+        -- Allowed characters, taken from ForSyde's mkVHDLExtId
+        allowed = ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ " \"#&\\'()*+,./:;<=>_|!$%@?[]^`{}~-"
+        strip_invalid = filter (`elem` allowed)
 
 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
                     -> AST.TypeMark -- ^ type of the vector
diff --git a/VHDL.hs b/VHDL.hs
index 99aa089..08375b7 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -311,13 +311,15 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do
                   return [AST.CSSASm assign]
               Right genBuilder ->
                 let
+                  ty = Var.varType bndr
+                  len = tfvec_len ty 
                   sigs = map varBndr valargs
                   signature = Maybe.fromMaybe
                     (error $ "Using function '" ++ (bndrToString (head sigs)) ++ "' without signature? This should not happen!") 
                     (Map.lookup (head sigs) signatures)
                   arg_names = map (mkVHDLExtId . bndrToString) (tail sigs)
                   dst_name = mkVHDLExtId (bndrToString bndr)
-                  genSm = genBuilder 4 signature (arg_names ++ [dst_name])  
+                  genSm = genBuilder len signature (arg_names ++ [dst_name])  
                 in return [AST.CSGSm genSm]
           else
             error $ "VHDL.mkConcSm Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ pprString valargs