From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Thu, 9 Apr 2009 16:29:53 +0000 (+0200)
Subject: Generalize VHDL type creation for SizedWord and FSVec.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=eb685a2f6743bfea37ef304cad0129e16c2809ee;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Generalize VHDL type creation for SizedWord and FSVec.
---

diff --git a/CoreTools.hs b/CoreTools.hs
index 06b7a62..3d3828b 100644
--- a/CoreTools.hs
+++ b/CoreTools.hs
@@ -69,3 +69,11 @@ eval_type_level_int ty =
 
     core <- toCore [] app
     execCore core 
+
+-- | Get the length of a FSVec type
+fsvec_len :: Type.Type -> Int
+fsvec_len ty =
+  eval_type_level_int len
+  where 
+    (tycon, args) = Type.splitTyConApp ty
+    [len, el_ty] = args
diff --git a/VHDL.hs b/VHDL.hs
index 8ae3516..67ef0c7 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -370,7 +370,7 @@ vhdl_ty ty = do
             (tycon, args) <- Type.splitTyConApp_maybe ty
             let name = Name.getOccString (TyCon.tyConName tycon)
             case name of
-              "FSVec" -> Just $ mk_fsvec_ty ty args
+              "FSVec" -> Just $ mk_vector_ty (fsvec_len ty) ty
               "SizedWord" -> Just $ mk_vector_ty (sized_word_len ty) ty
               otherwise -> Nothing
       -- Return new_ty when a new type was successfully created
@@ -378,25 +378,6 @@ vhdl_ty ty = do
         (error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty))
         new_ty
 
--- | Create a VHDL type belonging to a FSVec Haskell type
-mk_fsvec_ty ::
-  Type.Type -- ^ The Haskell type to create a VHDL type for
-  -> [Type.Type] -- ^ Type arguments to the FSVec type constructor
-  -> TypeState AST.TypeMark -- The typemark created.
-
-mk_fsvec_ty ty args = do
-  -- Assume there are two type arguments
-  let [len, el_ty] = args 
-  let len_int = eval_type_level_int len
-  let ty_id = mkVHDLExtId $ "vector_" ++ (show len_int)
-  -- TODO: Use el_ty
-  let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len_int - 1))]
-  let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty
-  let ty_dec = AST.TypeDec ty_id ty_def
-  -- TODO: Check name uniqueness
-  State.modify (Map.insert (OrdType ty) (ty_id, ty_dec))
-  return ty_id
-
 -- | Create a VHDL vector type
 mk_vector_ty ::
   Int -- ^ The length of the vector