From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Fri, 19 Jun 2009 10:41:49 +0000 (+0200)
Subject: Add another higher order testcase, highordtest2.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=eb3177ed5e53fd27bc64a45584ab646545c27e5f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Add another higher order testcase, highordtest2.

This testcase can be succesfully normalized and translated to VHDL.
---

diff --git a/Adders.hs b/Adders.hs
index 2ee1de6..d4dbbf8 100644
--- a/Adders.hs
+++ b/Adders.hs
@@ -165,6 +165,16 @@ highordtest = \x ->
              in
                 \c d -> op' d c
 
+highordtest2 = \a b ->
+         case a of
+           High -> \c d -> d
+           Low -> let
+             op' :: Bit -> Bit -> Bit
+             op' = case b of
+                High -> \c d -> d
+                Low -> \c d -> c
+             in
+                \c d -> op' d c
 -- Four bit adder, using the continous adder below
 -- [a] -> [b] -> ([s], cout)
 --con_adder_4 as bs = 
diff --git a/Translator.hs b/Translator.hs
index 3f60330..7b548e7 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -53,7 +53,7 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
-  makeVHDL "Adders.hs" "highordtest" True
+  makeVHDL "Adders.hs" "highordtest2" True
 
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do