From: Christiaan Baaij Date: Sun, 21 Mar 2010 21:41:38 +0000 (+0100) Subject: Fix gencopy' to use proper vhdl names X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=e9462bb7914eb28bea85f13383e0224802187fda;hp=25b6c1ebc720fda83104b93d4a24ad8dde4d71a5;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Fix gencopy' to use proper vhdl names --- diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs" index a6f3590..fd26365 100644 --- "a/c\316\273ash/CLasH/VHDL/Generate.hs" +++ "b/c\316\273ash/CLasH/VHDL/Generate.hs" @@ -814,15 +814,15 @@ genUnzip' (Left res) f args@[arg] = do _ -> error $ "Unzipping a value that is not a vector? Value: " ++ pprString arg ++ "\nType: " ++ pprString (Var.varType arg) ++ "\nhtype: " ++ show htype genCopy :: BuiltinBuilder -genCopy = genNoInsts $ genVarArgs genCopy' -genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm] -genCopy' (Left res) f args@[arg] = - let - resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others) - (AST.PrimName (varToVHDLName arg))] - out_assign = mkUncondAssign (Left res) resExpr - in - return [out_assign] +genCopy = genNoInsts genCopy' +genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.ConcSm] +genCopy' (Left res) f [arg] = do { + ; [arg'] <- argsToVHDLExprs [arg] + ; let { resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others) arg'] + ; out_assign = mkUncondAssign (Left res) resExpr + } + ; return [out_assign] + } genConcat :: BuiltinBuilder genConcat = genNoInsts $ genVarArgs genConcat'