From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Thu, 20 Aug 2009 12:22:09 +0000 (+0200)
Subject: Connect resetn port to states.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=e5dd5cf96b276f6a3e480a6b1d2214f3701fa5dc;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Connect resetn port to states.

Atleast initial state can now easily be added manual.
Be sure to update to the latest 'vhdl' package as the
old one incorrectly pretty printed the "elsif" keyword
---

diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs"
index d1bf375..5881007 100644
--- "a/c\316\273ash/CLasH/VHDL/Generate.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Generate.hs"
@@ -167,16 +167,18 @@ mkStateProcSm ::
 mkStateProcSm (old, new) = do
   nonempty <- hasNonEmptyType old 
   if nonempty 
-    then return [AST.CSPSm $ AST.ProcSm label [clk] [statement]]
+    then return [AST.CSPSm $ AST.ProcSm label [clockId,resetId] [statement]]
     else return []
   where
     label       = mkVHDLBasicId $ "state"
-    clk         = mkVHDLBasicId "clock"
     rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
     wform       = AST.Wform [AST.WformElem (AST.PrimName $ varToVHDLName new) Nothing]
-    assign      = AST.SigAssign (varToVHDLName old) wform
-    rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
-    statement   = AST.IfSm rising_edge_clk [assign] [] Nothing
+    clk_assign      = AST.SigAssign (varToVHDLName old) wform
+    rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clockId)]
+    resetn_is_low  = (AST.PrimName $ AST.NSimple resetId) AST.:=: (AST.PrimLit "'0'")
+    reset_statement = []
+    clk_statement = [AST.ElseIf rising_edge_clk [clk_assign]]
+    statement   = AST.IfSm resetn_is_low reset_statement clk_statement Nothing
 
 
 -- | Transforms a core binding into a VHDL concurrent statement