From: Matthijs Kooijman Date: Tue, 10 Mar 2009 16:58:07 +0000 (+0100) Subject: Add a TODO. X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=e0db471a3cc20af68785dfe321b8eb3db6fa1b9d;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Add a TODO. --- diff --git a/VHDL.hs b/VHDL.hs index 572e221..c952ddd 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -375,6 +375,7 @@ mk_fsvec_ty ty args = do let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "16")] let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty let ty_dec = AST.TypeDec ty_id ty_def + -- TODO: Check name uniqueness State.modify (Map.insert (OrdType ty) (ty_id, ty_dec)) return ty_id