From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Mon, 29 Jun 2009 13:06:34 +0000 (+0200)
Subject: Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=d9fdace4c79166836aaa00d7cfa5541f2dc29c3f;hp=-c;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Merge branch 'cλash' of git.stderr.nl/matthijs/projects/master-project

* 'cλash' of http://git.stderr.nl/matthijs/projects/master-project:
  Make genMap support mapping applications.
  Allow arguments to builtins to be applications.
---

d9fdace4c79166836aaa00d7cfa5541f2dc29c3f
diff --combined Generate.hs
index 3e3a21d,3c5705a..e6a5d45
--- a/Generate.hs
+++ b/Generate.hs
@@@ -84,9 -84,11 +84,11 @@@ genFCall' (Right name) _ _ = error $ "C
  
  -- | Generate a generate statement for the builtin function "map"
  genMap :: BuiltinBuilder
- genMap = genVarArgs genMap'
- genMap' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
- genMap' (Left res) f [mapped_f, arg] =
+ genMap (Left res) f [Left mapped_f, Left (Var arg)] =
+   -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL
+   -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since
+   -- we must index it (which we couldn't if it was a VHDL Expr, since only
+   -- VHDLNames can be indexed).
    let
      -- Setup the generate scheme
      len         = (tfvec_len . Var.varType) res
@@@ -102,7 -104,9 +104,9 @@@
      resname     = mkIndexedName (varToVHDLName res) n_expr
      argexpr     = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
    in do
-     app_concsms <- genApplication (Right resname) mapped_f [Right argexpr]
+     let (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f
+     let valargs = get_val_args (Var.varType real_f) already_mapped_args
+     app_concsms <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr])
      -- Return the generate statement
      return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
  
@@@ -374,7 -378,6 +378,7 @@@ genUnconsVectorFuns elemTM vectorTM  
    , (selId, AST.SubProgBody selSpec  [AST.SPVD selVar] [selFor, selRet])
    , (ltplusId, AST.SubProgBody ltplusSpec [AST.SPVD ltplusVar] [ltplusExpr, ltplusRet]  )  
    , (plusplusId, AST.SubProgBody plusplusSpec [AST.SPVD plusplusVar] [plusplusExpr, plusplusRet])
 +  , (lengthTId, AST.SubProgBody lengthTSpec [] [lengthTExpr])
    ]
    where 
      ixPar   = AST.unsafeVHDLBasicId "ix"
@@@ -608,9 -611,6 +612,9 @@@
                       ((AST.PrimName $ AST.NSimple vec1Par) AST.:&: 
                        (AST.PrimName $ AST.NSimple vec2Par))
      plusplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
 +    lengthTSpec = AST.Function (mkVHDLExtId lengthTId) [AST.IfaceVarDec vecPar vectorTM] naturalTM
 +    lengthTExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NAttribute $ 
 +                                AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))
  
  -----------------------------------------------------------------------------
  -- A table of builtin functions
@@@ -641,7 -641,6 +645,7 @@@ globalNameTable = Map.fromLis
    , (emptyId          , (0, genFCall                ) )
    , (singletonId      , (1, genFCall                ) )
    , (copyId           , (2, genFCall                ) )
 +  , (lengthTId        , (1, genFCall                ) )
    , (hwxorId          , (2, genOperator2 AST.Xor    ) )
    , (hwandId          , (2, genOperator2 AST.And    ) )
    , (hworId           , (2, genOperator2 AST.Or     ) )