From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Tue, 23 Jun 2009 20:55:53 +0000 (+0200)
Subject: Always use everything declared in VHDL work library
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=d3cb6d2f0f875a77483348a8003074e8d77a3198;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Always use everything declared in VHDL work library
---

diff --git a/VHDL.hs b/VHDL.hs
index 8d36af7..1f08abe 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -63,7 +63,8 @@ createDesignFiles binds =
       ]
     full_context =
       mkUseAll ["work", "types"]
-      : ieee_context
+      : (mkUseAll ["work"]
+      : ieee_context)
     type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ vec_decls ++ ty_decls ++ subProgSpecs)
     type_package_body = AST.LUPackageBody $ AST.PackageBody typesId (concat tyfun_decls)
     subProgSpecs = concat (map subProgSpec tyfun_decls)