From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Tue, 25 Aug 2009 13:12:00 +0000 (+0200)
Subject: Add slide with complete signature, including context, of registerBank
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=ce4726310e0e0586d352338c1e5786758ffe05fd;p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git

Add slide with complete signature, including context, of registerBank
---

diff --git a/PolyAlu.lhs b/PolyAlu.lhs
index 63f6d89..55b000d 100644
--- a/PolyAlu.lhs
+++ b/PolyAlu.lhs
@@ -56,13 +56,13 @@ type Word           =   SizedInt D12
 {
 We make a primitive operation:
 \begin{code}
-primOp :: {-"{\color<2>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
+primOp :: {-"{\color<3>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
 primOp f a b = a `f` a
 \end{code}\pause
 We make a vector operation:
 \begin{code}
-vectOp :: {-"{\color<2>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
-vectOp f a b = {-"{\color<2>[rgb]{1,0,0}"-}foldl{-"}"-} f a b
+vectOp :: {-"{\color<3>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
+vectOp f a b = {-"{\color<3>[rgb]{1,0,0}"-}foldl{-"}"-} f a b
 \end{code}
 }
 \subsection{Polymorphic, Higher-Order ALU}
@@ -85,15 +85,15 @@ Make a simple register bank:
 \begin{code}
 registerBank :: 
   CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
-  (RegState s a) -> a -> {-"{\color<2>[rgb]{1,0,0}"-}RangedWord s{-"}"-} ->
-  {-"{\color<2>[rgb]{1,0,0}"-}RangedWord s{-"}"-} -> Bit -> ((RegState s a), a )
+  (RegState s a) -> a -> RangedWord s ->
+  RangedWord s -> Bit -> ((RegState s a), a )
   
 registerBank (State mem) data_in rdaddr wraddr wrenable = 
   ((State mem'), data_out)
   where
     data_out  =   mem!rdaddr
-    mem'  {-"{\color<3>[rgb]{1,0,0}"-}| wrenable == Low{-"}"-}    = mem
-          {-"{\color<3>[rgb]{1,0,0}"-}| otherwise{-"}"-}          = replace mem wraddr data_in
+    mem'  {-"{\color<2>[rgb]{1,0,0}"-}| wrenable == Low{-"}"-}    = mem
+          {-"{\color<2>[rgb]{1,0,0}"-}| otherwise{-"}"-}          = replace mem wraddr data_in
 \end{code}
 }
 \subsection{Simple CPU: ALU \& Register Bank}
diff --git a/clash-haskell09.pdf b/clash-haskell09.pdf
index 5efe7ed..051f90d 100644
Binary files a/clash-haskell09.pdf and b/clash-haskell09.pdf differ
diff --git a/introduction.lhs b/introduction.lhs
index 899c534..5cd6c0a 100644
--- a/introduction.lhs
+++ b/introduction.lhs
@@ -53,7 +53,7 @@ mealyMachine ::
   (State, OutputSignals)
 mealyMachine inputs {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} = ({-"{\color<3>[rgb]{1,0,0}"-}new_state{-"}"-}, output)
   where
-    {-"{\color<3>[rgb]{1,0,0}"-}new_state{-"}"-}   =   logic     {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-}   input
+    {-"{\color<3>[rgb]{1,0,0}"-}new_state{-"}"-}    =   logic     {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-}   input
     outputs                                         =   logic     {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-}   input
 \end{code}
 }
@@ -65,7 +65,7 @@ mealyMachine inputs {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} = ({-"{\color<3>[rg
 run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} [] = []
 run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} (i:input) = o:out
   where
-    ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o) = func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} i
-    out         = run func {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input
+    ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o)  =   func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} i
+    out                                             =   run func {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input
 \end{code}
 }
\ No newline at end of file
diff --git a/summery.lhs b/summery.lhs
index 1383d55..49248a4 100644
--- a/summery.lhs
+++ b/summery.lhs
@@ -1,3 +1,4 @@
+%include talk.fmt
 \section{Conclusion}
 
 \frame{
@@ -11,6 +12,19 @@
 
 \frame{
 \begin{figure}
-\Large{Thank you for listening}
+\Huge{Thank you for listening}
 \end{figure}
+}
+
+\frame
+{
+\frametitle{Complete signature for registerBank}
+\begin{code}
+registerBank :: 
+  ( NaturalT s
+  , PositiveT (s :+: D1)
+  , ((s :+: D1) :>: s) ~ True )) =>
+  (RegState s a) -> a -> RangedWord s ->
+  RangedWord s -> Bit -> ((RegState s a), a )
+\end{code}
 }
\ No newline at end of file